Reza Sotudeh reports on the struggle to design smaller, faster and
more efficient processors for next-generation
At the heart of almost all modern entertainment systems there are a handful of digital integrated circuits, at the core of which is a microprocessor switching at hundreds of millions of times per second. At this summer's Hot Chips conference in Stanford, California, technologists presented a host of newly designed "media processors" for the new audiovisual gadgets.
The burden on such processors increases as they have to perform more work on richer content. The chips must also recover from errors fast enough to avoid irritating the consumer.
Performance can be boosted by applying narrowly focused optimisation techniques to highly specialised processor architectures for specific applications. But my research team rapidly discovered the drawback of this: it restricts the applicability of the resulting architecture. And wide applicability is of key importance for integration of services and tools.
In a world where personal stereos, handheld TVs and cellular phones are commonplace, designing new products that fail to link or integrate with other high-tech gadgets may not be a good idea.
The consumer is already faced with the dilemma of investing in a whole host of home entertainment systems, particularly in the area of television. The government intends to switch off analogue TV broadcasts before the end of the next decade. Switching to digital brings more channels and enhanced services. However, this may not be sufficient incentive for the consumer to invest in a new TV set, unless the new set brings added value to the household. As a sweetener for the transition from analogue to digital, the government is considering offering some of its own services to digital TV owners via the internet.
Television transmissions are currently composed of interlaced video frames, coded audio streams for cinema-effect sound and indexed teletext pages.
Adding yet more services to the humble box will inevitably demand more switching power from the core processor, and as some of these additional chores are as computationally intensive as the standard ones, it is not surprising that processor clock rates have increased by up to 40 per cent per year in recent years. In a digital TV system handling a 625-line signal (the existing analogue standard), the core processing unit will have to perform up to 1,000 operations per pixel, on a picture comprising 625 rows of 864 pixels, at a rate of 25 frames per second. This translates to 13.5 billion operations per second.
The designers of processors for advanced digital TVs must now consider how they can also incorporate algorithms to improve picture sharpness, reduce noise, de-interlace and convert to multiple video formats.
All that is relatively simple. Modern digital TVs must also perform motion-estimation by detecting movement in the picture frame, and error concealment when picture frames/lines are lost during transmission, in order to maintain the quality of service to the viewer. Add the growing number of personal peripherals and portable units such as PDAs and camcorders that are linked via telephone lines, infra-red, wireless and other communication methods. All these are potentially able to link into the services delivered by digital television.
As services converge, more processing performance will be required and as the need for personal and portable communication, entertainment and productivity tools increases, these processors will have to consume less power.
The market has already shown that for such products to have mass appeal, they have to be priced under Pounds 100.
Price-performance factors have always played a role in new products, but as the next decade sees a new generation of digital technologies hit the market, the processor designers will be grappling with cramming more services into their architectures, fitting them into smaller spaces and trying to push production yields up to reduce cost.
Reza Sotudeh is head of the department of electronic, communications and electrical engineering at the University of Hertfordshire.