Principal Performance Architect

Explore the performance of next generation supercomputers using hardware-software codesign

The Compute System Architecture Unit (CSA) at imec is researching next-generation large-scale heterogeneous computer architectures for next-generation HPC and AI applications, such as real-time digital twins. The team is responsible for algorithm research, runtime management innovations, performance modeling, architecture simulation and prototyping for these future applications and the future systems to execute them, to reach multiple orders of magnitude better performance, energy-efficiency, and total-cost-of-ownership. 

We are looking for a Principal Performance Architect to technically drive performance analysis across multiple layers, from algorithm definition to microarchitecture implementation. You will work closely with experts from those different fields to build the evaluation infrastructure required to evaluate the impact of codesign innovations. This position plays a key role in our desire to shape the future of supercomputer architecture

Your responsibilities include:

• Lead development of performance models that combine software and hardware properties at various level of detail, analyze results and develop optimization algorithms to explore the large design space and to improve runtime scheduling.
• Lead development of performance analysis tools and frameworks that capture the relevant application characteristics at either design time, compile time or runtime to feed into the performance models
• Connect research from algorithms, resource management, firmware, system architecture, and microarchitecture to evaluate the benefit of proposed solutions.