Institute for Communication Systems

Location: Guildford
Salary: £42,149 to £50,296 per annum
Fixed Term
Post Type: Full Time
Closing Date: 23.59 hours BST on Sunday 23 October 2022
Reference: 023222-R-R

The Institute for Communication Systems (ICS) home of the 5G and 6G Innovation Centre (5GIC/6GIC) is looking to recruit a Research FPGA Developer in Digital Design for Advanced Communication Systems. The successful candidate will be part of the Wireless Systems Lab group and will have the opportunity to work very close with our industrial partners as well as with academic partners all over the world.

The successful candidate will be part of a group that focuses on advanced signal processing architectures for future communication systems and their efficient realization (i.e., algorithmic/architectural co-design), as well as on experimentation and concept validation via software defined radios. The post holder will be expected to design, develop and validate efficient hardware architectures for current and future communication systems, mainly targeting physical layer functionality. Displaying a high degree of autonomy, the successful candidate will find novel solutions to complex problems, as defined by standardisation committees and the Wireless Systems Lab group. The post holder will be expected to be able to set, define and work towards achieving targets, disseminate results and document work done.

ICS is the largest academic research institute in Europe specialising in all aspects of ICT (Information and Communication Technologies). It is home to over 200 researchers with expertise in all communication and broadcasting systems and has developed the best in class large scale testbeds for research and innovation and enjoys the state-of-the-art lab and computing facilities.

Established in 2012, 5GIC is the world’s first dedicated centre in researching end-to-end aspects of 5G and works closely with national and international leading academic institutes and key industrial partners. In November 2020, 6GIC was officially launched with parallel research undertaken in both 5G+ and 6G for 2030+.

The post holder must have expertise in the following:

• Design and development of physical layer digital signal processing algorithms targeting high throughput and low-latency on Xilinx FPGAs using RTL.

The post holder must also have at least one of the following:

• Recent experience in the development of complex signal processing algorithms and algorithmic architectures.
• Good understanding of signal processing for wireless communication systems. 
• An overall working knowledge of cellular networks (e.g.,: LTE, 5GNR).

It would be desirable but not essential for the post holder to also have:

• Experience with a high-speed FPGA protocol, e.g., PCIe or 10GE.
• Experience with HLS design methodologies (e.g., using Xilinx System Generator for DSP)
• Experience in high-performance programming targeting signal processing algorithms for high throughput and low-latency using C/C++ on x86 architectures
• Experience in programming on nVIDIA GPUs using the CUDA API.
• Prior experience with wireless research platforms (e.g., Open Air Interface with USRPs).

For informal enquiries please contact: Dr Konstantinos Nikitopoulos (k.nikitopoulos@surrey.ac.uk)

Further details: Job Description

Please note, it is University Policy to offer a starting salary equivalent to Level 3.6 (£32,344) to successful applicants who have been awarded, but are yet to receive, their PhD certificate. Once the original PhD certificate has been submitted to the local HR Department, the salary will be increased to Level 4.1 (£33,309).